1. Field of the Invention
This invention relates to the field of semiconductor devices and more particularly to semiconductor devices having a conduction enhancement layer.
2. Description of Related Art
Semiconductor devices are increasingly required to accommodate high currents and/or high voltages without failing. Many high power applications call for the use of a semiconductor switch which is required to conduct a large current when turned on, and to block a high voltage when off.
One device used in such applications is the power metal-oxide-semiconductor field-effect transistor (MOSFET). As discussed in J. Baliga, Power Semiconductor Devices, PWS Publishing Co. (1996) at p. 426, a power MOSFET exhibits excellent fast switching capability and safe-operating-area. When designed to block relatively low voltages (less than 200 volts), the power MOSFET has a low on-resistance. However, on-resistance increases very rapidly when its breakdown voltage is increased. This makes the on-state power losses unacceptable where high DC supply voltages are used.
Another approach which has been explored to improve blocking voltage while maintaining low on-resistance has been the fabrication of FETs using silicon carbide (SiC). SiC has a wider bandgap than does silicon (Si), giving it a “critical electric field”—i.e., the peak electric field that a material can withstand without breaking down—that is an order of magnitude higher than that of Si. This allows much higher doping and a much thinner drift layer for a given blocking voltage, resulting in a very low specific on-resistance in SiC-based devices.
Unfortunately, many SiC devices developed to date exhibit severe commercialization constraints. One such device is described in “High-voltage Accumulation-Layer UMOSFET's in 4H-SiC”, IEEE Electron Device Letters, Vol. 19, No. 12 (December 1998), pp. 487-489. This SiC-based device employs a UMOS structure, with an accumulation channel formed on the sidewalls of the trench by epitaxial growth to attain enhancement mode operation. It requires an additional epitaxial layer under the p-base to promote current spreading and achieve low on-resistance. The doping levels and the thicknesses of the sidewall epilayer and the epilayer under the p-base must be tightly controlled to achieve an enhancement mode device with low on-resistance. These demands result in a complex fabrication process which is unsuitable for large-scale manufacturing.
Another high power device is the insulated-gate bipolar transistor (IGBT). An IGBT with a trench gate structure is described, for example, in H.-R. Chang and B. Baliga, “500-V n-Channel Insulated-Gate Bipolar Transistor with a Trench Gate Structure”, IEEE Transactions on Electron Devices, Vol. 36, No. 9, September 1989, pp. 1824-1828. In operation, a positive gate voltage forms N-type inversion layers, through which electrons flow to provide the base drive needed to turn on the device's PNP transistor.
However, the IGBT has disadvantages which render it unsuitable for some applications. Because the structure is basically a transistor with gain, there will be some recombination in its N− drift region, causing the device to exhibit a high forward voltage drop. Another drawback to IGBTs is that they can “latch-up”, at which point they are no longer under the control of the gate voltage. When in this mode, conduction through the device can no longer be controlled by the gate voltage.